Conventionally used output buffer circuits are, for example, as shown in FIG. 9, provided with a NOR gate NO that receives a data signal (in this figure, DATA) and an enable signal (in this figured, ENL), and an N channel MOS transistor Tx having its gate connected to the output of the NOR gate NO, its source grounded, and its drain fitted with an output terminal OUT. When such an output buffer circuit is used in a thermal print head, there is provided, as shown in FIG. 9, a heater resistance R that is connected, at one end thereof, to the output terminal OUT and receives, at the other end thereof, a voltage VH applied thereto.
The NOR gate NO in this output buffer circuit is configured as shown in FIG. 10. Specifically, there are provided a P channel MOS transistor T1 receiving a power supply voltage VDD applied to its source and receiving an enable signal at its gate, a P channel MOS transistor T2 having its source connected to the drain of the MOS transistor T1 and receiving a data signal at its gate, a MOS transistor T3 having its source grounded and receiving a data signal at its gate, and a MOS transistor T4 having its source grounded and receiving an enable signal at its gate. The drains of the MOS transistors T3 and T4 are connected to the drain of the MOS transistor T2, and the node at which the drains of the MOS transistors T2 to T4 are connected together serves as the output end and is connected to the gate of the MOS transistor Tx.
In this output buffer circuit, the gradient of voltage change appearing in the output terminal OUT varies depending on the gate capacitance of the gate of the MOS transistor Tx serving as a driver and the on-state resistances of the MOS transistors T1, T2, and T4. Specifically, the rate of voltage change appearing in the output terminal OUT becomes higher when the composite resistance of the on-state resistances of the MOS transistors T1 and T2 and the on-state resistance of the MOS transistor T4 are made lower, and it becomes lower when the composite resistance of the on-state resistances of the MOS transistors T1 and T2 and the on-state resistance of the MOS transistor T4 are made higher. In this way, by varying the magnitudes of the on-state resistances of the MOS transistors T1, T2, and T4 provided in the NOR gate NO, it is possible to adjust the gradient of the voltage change appearing in the output terminal OUT. This makes it possible to build an output buffer circuit that operates at an operation frequency at which to handle a data signal and an enable signal.
Moreover, as a conventional technique, there has been proposed an output buffer circuit that makes, by turning on the transistors having different on-state resistances and connected in parallel at different times to return an output, the output vary gently, and then changes the output sharply, and in addition adjusts times at which to switch the rate of output change by varying a threshold value of an inverter circuit that receives the returned output (see Japanese Patent Application Laid-Open No. 2001-292056). This output buffer circuit is provided with a buffer that delays a signal inputted from an input terminal VIN and an inverter that returns a signal outputted from an output terminal VOUT, and turns on/off the MOS transistor having low on-state resistance according to the output of the NAND gate that receives the outputs of the buffer and the inverter.
With this configuration, when the output from the output buffer circuit varies, there appears first a sharp change, then a signal delayed by the buffer is fed, and then the MOS transistor having low on-state resistance is turned off. This makes the output vary gently. Thereafter, when the output from the output terminal VOUT exceeds the threshold value of the inverter, the output from the inverter varies, turning on the MOS transistor having low on-state resistance. This makes the output vary sharply. That is, by adjusting the threshold value of the inverter, it is possible to change the length of time the output varies sharply. This makes it possible to build an output buffer circuit that operates at an operation frequency.
However, in the output buffer circuit configured as shown in FIG. 9 and the output buffer circuit disclosed in Patent Document 1, it is necessary to change the on-state resistances of the MOS transistors T1 and T4 provided in the NOR gate NO and the threshold value of the inverter according to the operation frequency at which the output buffer circuit operates. That is, in either case, the output buffer circuits are so configured as to operate at a predetermined operation frequency, and thus cannot be offered as a general-purpose output buffer. To solve this problem, conventionally, as shown in FIG. 11, NOR gates NO1 and NO2 are used that are configured as shown in FIG. 10 and provided with the MOS transistors T1 and T4 having different on-state resistances, making the operation frequency range wider.
Specifically, the output buffer circuit shown in FIG. 11 is provided with a transistor switch S1 that selects an output from the NOR gate NO1 in which the MOS transistors T1 and T4 have high on-state resistances, and a transistor switch S2 that selects an output from the NOR gate NO2 in which the MOS transistors T1 and T4 have low on-state resistances. A selection control signal for selecting one among the outputs from the NOR gates NO1 and NO2 is fed to the gate of the transistor switches S1 and S2, and then the output from the NOR gate NO1 or NO2 is inputted, via the transistor switches S1 and S2, to the gate of the MOS transistor Tx. The transistor switches S1 and S2 are each composed, as shown in FIG. 12, of an N channel MOS transistor Tn and a P channel MOS transistor To connected in parallel.
The selection control signal is inputted to the gate of the N channel MOS transistor Tn of the transistor switch S1 and to the gate of the P channel MOS transistor Tp of the transistor switch S2. Moreover, the selection control signal is inverted by the inverter Ix, and is then inputted to the gate of the P channel MOS transistor Tp of the transistor switch S1 and to the gate of the N channel MOS transistor Tn of the transistor switch S2.
When the operation frequency is low, the selection control signal is turned to a high level and the transistor switch S1 is turned on, whereby the output from the NOR gate NO1 is fed to the gate of the MOS transistor Tx. On the other hand, when the operation frequency is high, the selection control signal is turned to a low level and the transistor switch S2 is turned on, whereby the output from the NOR gate NO2 is fed to the gate of the MOS transistor Tx. In this way, with the configuration shown in FIG. 11, it is possible to build an output buffer circuit that easily varies an output according to the operation frequency by switching the selection control signal from one level to another.
However, when the output buffer circuit is configured as shown in FIG. 11, it is provided with the NOR gates NO1 and NO2 and the transistor switches S1 and S2, resulting in an increased size of the output buffer circuit compared with that of the output buffer circuit shown in FIG. 9 or disclosed in Patent Document 1. This makes it difficult to make smaller a semiconductor integrated circuit device provided with such an output buffer circuit. Furthermore, in a thermal print head or the like provided with such a semiconductor integrated circuit device, the number of output buffer circuits is determined according to the number of print bits. Thus, the device size is further increased by a factor of the number of print bits.